2.1 Super-FinSim directory structure 2
2.2 Super-FinSim installation guide 2
2.2.1 Installing the UNIX distribution 2
3.1 Operations performed by the compiler 7
3.2 Invoking the Verilog Compiler 7
3.2.1 Verilog Compiler Options 8
3.2.2 Precedence order for simulation mode options 16
3.3 Files generated by the Verilog compiler finvc 16
3.4 Incremental recompilation 17
3.5.1 Compiling a Verilog Design Hierarchy into object code for later reuse 17
3.5.2 Using a separately compiled hierarchy 18
3.6 Calling user C tasks/functions in Super-FinSim without the PLI interface 19
3.7 Using Mixed Verilog/SysytemC descriptions 19
3.7.1 3.7.2 Instantiating SystemC modules in Verilog 20
3.7.2 3.7.3 Invoking finvc when there are SystemC modules involved 20
3.7.3 3.7.4 Rules to be observed by SystemC modules instantiated in Verilog: 20
3.7.4 3.7.5 Invoking TOP.sim or the name of the simulator 20
4.1 Operations performed by the simulation builder 21
4.2 Invoking the simulation builder 22
5.1 Using the Fintronic PLI table 23
5.1.1 Creating the table manually 23
5.1.2 Creating the table automatically 25
5.2 Building a custom compiler 25
6.3.2 Interactive Simulation 30
6.3.4 The Save and Restart feature in Super-FinSim. 30
6.4 Starting a real time waveform display 32
6.6 Interrupting the simulator 33
6.7 Terminating the simulator 33
7.1 List of interactive commands 33
7.2 Processing simulation data structures 37
7.4 Handling of simulation scope 38
7.5 Querying of simulation objects 38
7.6 Super-FinSim environment variables 39
7.7 Miscellaneous system facilities 40
8.2 Variable Precision Fixed Point and Floating Point Support in Super-FinSim 43
8.5.2 Setting the fields of the descriptor 45
8.5.3 The Default Descriptor 47
8.6 VP register manipulation 47
8.6.1 Simple Assignments toVP registers 47
8.6.2 Arithmetic Operators operating on VP registers 48
8.6.4 Logical Operators involving VP registers 50
8.6.5 Assignments to non-VP objects 50
8.6.6 Trigonometric Direct and Inverse Functions 50
8.6.7 Hyperbolic direct and Inverse Functions 51
8.6.8 Functions returning universal constants 52
8.6.9 Logarithm and Exponential Functions 52
8.6.10 Assignments to VP registers of Complex Expressions involving VP registers 54
8.6.11 Using Special Condition Signals/Flags of VP registers 54
8.6.12 Assigning VP registers to verilog registers 54
8.6.13 Assigning Verilog Real to Verilog registers 54
8.6.14 Displaying VP register values 55
8.7 Cartesian and Polar types 55
8.7.5 Operators on Cartesian and Polar types 56
8.8 Operators on Multi-dimensional arrays 56
8.8.1 Populating Multi-dimensional arrays with values 57
8.8.2 Viewing elements of a multi-dimensional array as part of a different structure 58
9.1 Running Super-FinSim in pure interpreted mode 61
9.2 Running Super-FinSim in mixed mode 61
10.1 Super-FinSim status codes and errors 64
11.2 Code Coverage Information 66
12.1 Running Super-FinSim with Specman 67
12.1.1 Verilog Compilation. 68
12.1.2 Building the simulator. 68
12.1.3 Running the simulation. 69